-------------------------------------------------------------------------------
-- circuito_0_wrapper.vhd
-------------------------------------------------------------------------------
library IEEE;
use IEEE.STD_LOGIC_1164.ALL;

library UNISIM;
use UNISIM.VCOMPONENTS.ALL;

library circuito_v1_00_a;
use circuito_v1_00_a.all;

entity circuito_0_wrapper is
  port (
    dato_listo : in std_logic;
    entrada_circuito : in std_logic_vector(0 to 31);
    salida_circuito : out std_logic_vector(0 to 31)
  );
end circuito_0_wrapper;

architecture STRUCTURE of circuito_0_wrapper is

  component circuito is
    port (
      dato_listo : in std_logic;
      entrada_circuito : in std_logic_vector(0 to 31);
      salida_circuito : out std_logic_vector(0 to 31)
    );
  end component;

begin

  circuito_0 : circuito
    port map (
      dato_listo => dato_listo,
      entrada_circuito => entrada_circuito,
      salida_circuito => salida_circuito
    );

end architecture STRUCTURE;

